Impact of Technology Trends on Single Event Upset Resistance of CMOS SRAM

MOS transistors with channel length ranging from submicron to ultra-deep submicron were simulated with TCAD process simulator. Single event upset (SEU) critical charge (Q_crit) and LET threshold (LET_th) were calculated for each SRAM which was composed of these transistors, and an analysis formula between critical charge and LET_th was built up. The variety of Q_crit and LET_th with channel length scaling was investigated. The results show that Q_crit decreases as channel length scaling down and efficiency of charge collection in SEU increases because of parasitic bipolar transistor mechanism. As a result, LET_th decreases rapidly and SEU resistance of CMOS SRAMs weakens greatly.