Design of Multi-channel Front-end Readout Electronics Applied for New Plastic Scintillator Array Detector

The circuit and control logic design for new front-end readout electronics (FEE), which was based on a kind of ASIC chip and field-programmable gate array (FPGA), was described in this paper. The FEE was mainly applied in a new plastic scintillator array detector and it can sample, process and filtrate the 360 channels of analog signals from the new plastic scintillator array detector, then package and upload data from the detector to the data acquisition system (DAQ) through the LVDS differential interface. Meanwhile, with the circuits of linearity calibration for each channel, monitoring current of power supply, temperature of key devices and FPGA’s status parameters, the FEE has a set of useful functions and strong ability of self-protection.