Micro-beam and Broad-beam Experimental Research of Multiple-cell Upset in 65 nm Dual-well CMOS SRAM

The heavy-ion micro-beam experiment and broad-beam experiment were performed in two 65 nm dual-well CMOS static random access memories (SRAMs) in normal incident angle, respectively. Single event upset (SEU) cross section and the main physical mechanisms of multiple-cell upset (MCU) were investigated by combining MCU pattern, position and counts with the memory cell array layout. The results show that the micro-beam spot is small and uniform, which makes sure that the ions do not hit the peripheral circuits. The ratio of MCU caused by NMOS transistor and the total SEU events is up to 32%, which indicates the charge sharing between NMOS transistors can not be ignored, while there’s no MCU caused by PMOS transistor during the tests, which infers that the high density well contact can inhibit the charge sharing between PMOS transistors effectively. Moreover, reducing the spacing between the drain and the N-well/P-well interface can lessen the probability of SEU. While reducing the spacing between the same kind of transistors in a memory cell as well as increasing the spacing between the same kind of transistors of adjacent memory cells can also weaken the charge sharing, which leads to less MCU.