Research on High Performance Campbell Algorithm Based on FPGA

To meet the wide measuring range requirement of ITER neutron flux monitor, a high performance digital Campbell integrator based on FPGA and the AC-coupling square integration method was developed, which extends the measuring upper range from 10⁵ s^-1 of the counting method to 10⁸ s^-1 and shows high precision. The digital Campbell algorithm was studied based on the principle of ²³⁵U fission chamber and Campbell theorem. By implementing an experiment using imitative neutron pulses, the performance of counting method and Campbell algorithm in the overlapped section was analyzed. The applicable conditions of Campbell algorithm under different noise levels were obtained to make the relative error less than 5%. Moreover, an in-situ experiment at HL-2A was carried out. The output of Campbell algorithm was fitted by the output of counting method and then converted to counting rate. The linear coefficient reaches 0.97 and the converted counting rate shows remarkable consistency with the result of counting method.