Design of Novel and Low Cost Triple-node Upset Self-recoverable Latch

BAI Na; MING Tianbo; XU Yaohua; WANG Yi; LI Yunfei; LI Li

doi:10.7538/yzk.2023.youxian.0625

Atomic Energy Science and Technology > 2023 > 57(12): 2326-2336. > DOI: 10.7538/yzk.2023.youxian.0625

BAI Na, MING Tianbo, XU Yaohua, WANG Yi, LI Yunfei, LI Li. Design of Novel and Low Cost Triple-node Upset Self-recoverable Latch[J]. Atomic Energy Science and Technology, 2023, 57(12): 2326-2336. DOI: 10.7538/yzk.2023.youxian.0625

Citation:

PDF (7763 KB)

Design of Novel and Low Cost Triple-node Upset Self-recoverable Latch

BAI Na^1,2,
MING Tianbo¹,
XU Yaohua¹,
WANG Yi^1,3,
LI Yunfei^1,3,
LI Li^2,3

1.
Information Materials and Intelligent Sensing Laboratory of Anhui Province, Anhui University, Hefei 230601, China
2.
Shanxi Key Laboratory of Advanced Semiconductor Optoelectronic Devices and Integrated Systems, Jincheng 048000, China
3.
Jincheng Research Institute of Opo-mechatronics Industry, Jincheng 048000, China

More Information

Graphical Abstract

Abstract

Abstract

With the development of semiconductor technology, the size of transistors continues to shrink. In complex radiation environments in aerospace and other fields, small-sized circuits are more prone to soft error (SE). Currently, single-node upset (SNU), double-node upset (DNU) and triple-node upset (TNU) caused by SE are relatively common. TNU’s solution is not yet fully mature. A novel and low-cost TNU self-recoverable latch (named NLCTNURL) was designed which is resistant to harsh radiation effects. When analyzing circuit resiliency, a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error occurs. Simulation results show that the latch has full TNU self-recovery. A comparative analysis was conducted on seven latches related to TNU. Besides, a comprehensive index combining delay, power, area and self-recovery—DPAN index was proposed, and all eight types of latches from the perspectives of delay, power, area, and DPAN index were analyzed and compared. The simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable, NLCTNURL is reduced by 68.23% and 57.46% respectively from the perspective of delay. From the perspective of power, NLCTNURL is reduced by 72.84% and 74.19%, respectively. From the area perspective, NLCTNURL is reduced by about 28.57% and 53.13%, respectively. From the DPAN index perspective, NLCTNURL is reduced by about 93.12% and 97.31%. The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.
- circuit reliability,
- latch design,
- self-recoverability,
- soft error,
- radiation hardening,
- triple-node upset

FullText(HTML)

References (17)

References

[1]	HUI X, YUN Z. Circuit and layout combination technique to enhance multiple nodes upset tolerance in latches［J］. IEICE Electronics Express, 2015, 12(9): 20150286.
[2]	FERLET-CAVROIS V, MASSENGILL L W, GOUKER P. Single event transients in digital CMOS—A review［J］. IEEE Transactions on Nuclear Science, 2013, 60(3): 1767-1790.
[3]	MESSENGER G C. Collection of charge on junction nodes from ion tracks［J］. IEEE Transactions on Nuclear Science, 1982, 29(6): 2024-2031.
[4]	SONG S, KIM Y. New power-efficient flip-flop based on a true single-phase clock and robust to single-node upsets［J］. IEIE Transactions on Smart Processing and Computing, 2021, 10(2): 167-175.
[5]	YAN A, HU Y, CUI J, et al. Information assurance through redundant design: A novel TNU error-resilient latch for harsh radiation environment［J］. IEEE Transactions on Computers, 2020, 69(6): 789-799.
[6]	YAN A, FENG X, HU Y, et al. Design of a triple-node-upset self-recoverable latch for aerospace applications in harsh radiation environments［J］. IEEE Transactions on Aerospace and Electronic Systems, 2019, 56(2): 1163-1171.
[7]	NICOLAIDIS M, PEREZ R, ALEXANDRESCU D. Low-cost highly-robust hardened cells using blocking feedback transistors［C］∥26th IEEE VLSI Test Symposium. USA: IEEE, 2008.
[8]	JAGANNATHAN S, LOVELESS T D, BHUVA B L, et al. Single-event tolerant flip-flop design in 40 nm bulk CMOS technology［J］. IEEE Transactions on Nuclear Science, 2011, 58(6): 3033-3037.
[9]	EBARA M, YAMADA K, KOJIMA K, et al. Process dependence of soft errors induced by alpha particles, heavy ions, and high energy neutrons on flip flops in FDSOI［J］. IEEE Journal of the Electron Devices Society, 2019, 7: 817-824.
[10]	YAN A, LING Y, CUI J, et al. Quadruple cross-coupled dual-interlocked-storage-cells-based multiple-node-upset-tolerant latch designs［J］. IEEE Transactions on Circuits and Systems I, 2020, 67(3): 879-890.
[11]	MULLER D E, BARTKY W S. A theory of asynchronous circuits［J］. Theory of Switching, 1959. doi: 10.1007/BF01069294.
[12]	EFTAXIOPOULOS N, AXELOS N, ZERVAKIS G, et al. Delta DICE: A double node upset resilient latch［C］∥2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS). USA: IEEE, 2015.
[13]	WATKINS A, TRAGOUDAS S. Radiation hardened latch designs for double and triple node upsets［J］. IEEE Transactions on Emerging Topics in Computing, 2017, 8(3): 616-626.
[14]	KUMAR C I, ANAND B. A highly reliable and energy-efficient triple-node-upset-tolerant latch design［J］. IEEE Transactions on Nuclear Science, 2019, 66(10): 2196-2206.
[15]	YAN A, LAI C, ZHANG Y, et al. Novel low cost, double-and-triple-node-upset-tolerant latch designs for nano-scale CMOS［J］. IEEE Transactions on Emerging Topics in Computing, 2018, 9(1): 520-533.
[16]	LIU X. Multiple node upset-tolerant latch design［J］. IEEE Transactions on Device and Materials Reliability, 2019, 19(2): 387-392.
[17]	LI H, XIAO L, LI J, et al. High robust and cost effective double node upset tolerant latch design for nanoscale CMOS technology［J］. Microelectronics Reliability, 2019, 93: 89-97.

Cited By

Get Citation

PDF

XML

Article views (43) PDF downloads (18)

Turn off MathJax

Article Contents

Abstract

References

Design of Novel and Low Cost Triple-node Upset Self-recoverable Latch

Abstract

References

Catalog

Export File

Citation

Format

Content