特征工艺尺寸对CMOS SRAM抗单粒子翻转性能的影响

Impact of Technology Trends on Single Event Upset Resistance of CMOS SRAM

摘要: 采用TCAD工艺模拟工具按照等比例缩小规则构建了从亚微米到超深亚微米级7种不同特征尺寸的MOS晶体管，计算了由这些晶体管组成的静态随机存储器(SRAM)单粒子翻转的临界电荷Q_crit、LET阈值(LET_th)，建立了LET_th与临界电荷之间的解析关系，研究了特征工艺尺寸对CMOS SRAM抗单粒子翻转性能的影响及原因。研究表明：随着特征尺寸的减小，SRAM单元单粒子翻转的临界电荷减小，电荷收集效率由于寄生双极晶体管效应而增加，造成LET_th随特征尺寸缩小而迅速减小，CMOS SRAM抗单粒子翻转性能迅速降低。

Abstract: MOS transistors with channel length ranging from submicron to ultra-deep submicron were simulated with TCAD process simulator. Single event upset (SEU) critical charge (Q_crit) and LET threshold (LET_th) were calculated for each SRAM which was composed of these transistors, and an analysis formula between critical charge and LET_thwas built up. The variety of Q_critand LET_th with channel length scaling was investigated. The results show that Q_crit decreases as channel length scaling down and efficiency of charge collection in SEU increases because of parasitic bipolar transistor mechanism. As a result, LET_thdecreases rapidly and SEU resistance of CMOS SRAMs weakens greatly.