[1] |
KOLASINSKI W A, KOGA R, SCHNAUSS E, et al. The effect of elevated temperature on latchup and bit errors in CMOS devices[J]. IEEE Trans Nucl Sci, 1986, 33: 1605-1609.
|
[2] |
TRUYEN D, BOCH J, SAGNES B, et al. Temperature effect on heavy-ion induced parasitic current on SRAM by device simulation: Effect on SEU sensitivity[J]. IEEE Trans Nucl Sci, 2007, 54: 1025-1029.
|
[3] |
COOPER M S, RETZLER J P. High temperature Schottky TTL latchup[J]. IEEE Trans Nucl Sci, 1978, 25: 1538-1544.
|
[4] |
STAPOR W J, JOHNSON R L, XAPSOS M A, et al. Single event upset dependence on temperature on an NMOS/resistive-load static RAM[J]. IEEE Trans Nucl Sci, 1986, 33: 1610-1615.
|
[5] |
MATTHEW J G, JONATHAN R A, BALAJI N, et al. Single-event transient measurements in nMOS and pMOS transistors in a 65 nm bulk CMOS technology at elevated temperatures[J]. IEEE Transactions on Device and Materials Reliability, 2011, 11: 179-186.
|
[6] |
LARID J S, HIRAO T, ONODA S, et al. Temperature dependency of heavy ion induced current transients in Si epilayer devices[J]. IEEE Trans Nucl Sci, 2002, 49: 1389-1395.
|
[7] |
GUO G, HIRAO T, LARID J S, et al. Temperature dependency of single event transient current by heavy ion microbeam on p+/n/n+ epilayer junctions[J]. IEEE Trans Nucl Sci, 2004, 51: 2834-2839.
|
[8] |
TRUYEN D, BOCH J, SAGNESS B, et al. Temperature effect on heavy-ion-induced single-event transient propagation in CMOS bulk 0.18 μm inverter chain[J]. IEEE Trans Nucl Sci, 2008, 55: 2001-2006.
|
[9] |
MATTHEW J G, JONATHAN R A, VISHWANATH R, et al. Temperature dependence of digital single-event transients in bulk and fully-depleted SOI technologies[J]. IEEE Trans Nucl Sci, 2009, 56: 3115-3121.
|
[10] |
MATTHEW J G, JONATHAN R A, BALAJI N, et al. Increased single-event transient pulsewidths in a 90 nm bulk CMOS technology operating at elevated temperatures[J]. IEEE Transactions on Device and Materials Reliability, 2010, 10: 157-163.
|
[11] |
CHEN S, LIANG B, LIU B, et al. Temperature dependency of digital SET pulse width in bulk and SOI technologies[J]. IEEE Trans Nucl Sci, 2007, 54: 889-893.
|
[12] |
LIU B, CHEN S, LIANG B, et al. Temperature dependency of charge sharing and MBU sensitivity in 130 nm CMOS technology[J]. IEEE Trans Nucl Sci, 2009, 56: 2473-2479.
|