Abstract: The irradiation tests were performed in a 65 nm triple-well CMOS static random access memory (SRAM) in normal incident angle by using four kinds of heavy ions with different linear energy transfer (LET) values. The single event upset (SEU) cross sections in upsets and in events and the main physical mechanisms of multiple cell upsets (MCUs) were investigated by combining MCUs pattern, position, and counts with the memory cell array layout. The results show that the SEU cross section in events is larger than the area of sensitive nodes in a memory cell while the SEU cross section in upsets is much larger than the area of a cell. The SEU cross section in upsets is larger than SEU cross section in events because of the significant increase in MCUs amount and order, and MCUs become the main source of SEU in SRAM. Moreover, considering of the vertical well isolation layout and the position of parasitic lateral bipolar transistors, most MCUs are induced by parasitic bipolar effect of PMOS and NMOS, of which the parasitic bipolar effect of NMOS is the main cause of MCUs.