Abstract: There are two reasons at least for integrated circuit (IC) failure or latent damage during transient dose rate radiation test. One is the thermal breakdown of metal interconnect caused by short time high current during latchup, and another is threshold-voltage shift due to oxide-trap charge induced by ionizing radiation. In this paper, the radiation effects of transient dose rate and steady ionization total dose were studied with 0.13 μm bulk silicon CMOS processor. The results show that the transient dose rate latchup effect induces significant latent damage in processor, which causes that the total dose failure threshold is reduced from 1 030 Gy(Si) to 600 Gy(Si). The result is important for device reliability estimate and radiation hardness design guideline.