Abstract: A circuit-level engineering approach to estimate single-event induced multiple-cell upset (MCU) characteristics in bulk CMOS SRAM was mainly presented in this paper. The proposed multinodes charge collection model could evaluate the bitupset cross sections in the layoutdesign process considering parasiticbipolar effects. The impact of different LETs and tilting angles of ion incidence on MCUs were studied and compared to experimental data for the devices manufactured by 65 nm technology.