Abstract: The large hadron collider (LHC) plans a series of upgrades to enter a higher luminosity phase in which the particle experiments are going to be more efficient. However, higher luminosity will introduce a lot of out-of-interest interactions, regarded as pile-up interactions, which are going to be a great challenge to the event reconstruction. To meet the challenges of the pile-up, in toroidal LHC apparatus (ATLAS) and compact muon solenoid (CMS) of the LHC, a new particle detection technique was proposed, which combines high resolution time measurement with position information. This technique will enhance the capability in event discrimination for pile-up mitigation, to make the event reconstruction more accuracy. Under this background, a novel silicon-based semiconductor detector called low-gain avalanche detector (LGAD), was expected to satisfy the requirements on high time precision and spatial resolution of millimeter pitch size, which also has application potentials in other particle physics experiment complexities. Considering the spatial density of the LGAD channels, an application specific integrated circuit (ASIC) with high granularity, instead of discreet component electronics, is indispensable for the high time precision readout. The ASIC was expected to integrate amplification, discrimination and time-to-digital conversion (TDC), to conduct high precision time measurement with digitized output in the front-end close to the detectors. As one of the collaborators of the ATLAS, a research group in University of Science and Technology of China (USTC) has been working on the LGAD study and testing. Meanwhile, a prototype ASIC for the LGAD readout has been designed and tested in the fast electronics laboratory of USTC. The analog part (including amplifier and discriminator) and the TDC part of the ASIC were researched, designed and tested independently, which will be integrated in one ASIC later after the verification. To meet the requirement of the time precision, the TDC was expected to reach a minimum bin size smaller than 20 ps and an RMS resolution better than 10 ps. And considering the minimum interval between two hit events in one channel, the conversion time (defined as the digitizing time consumption after the arrival of stop signal) of TDC should be smaller than 20 ns. For these design indexes, a dual-ring vernier structure was proposed for coarse-fine time measurement with “locked delay difference” in the vernier line, so that the requirements of TDC bin size, measurement range and conversion time were reached. Additionally, the ring structure largely optimizes the circuit area. During the TDC design, the structure of the delay cell, phase detector (and also the TDC arbiter), DLL and its charge pump were studied and optimized for better performance. The test results indicate that the TDC successfully reaches a bin size around 15 ps and an RMS resolution better than 10 ps, which meets the design indexes well.