Abstract: In order to investigate the influence of heavy ion fluence on single event upsets (SEU) and the SEU cross-section in NAND Flash memory, as well as the multiple-cell upsets (MCU) due to heavy ion irradiation, experimental studies were performed on two types of 25 nm NAND Flash memory devices. These experiments were conducted at the HI-13 Tandem Accelerator at the China Institute of Atomic Energy and the Heavy Ion Research Facility in Lanzhou (HIRFL). The experiment results revealed that bit upsets were randomly distributed across addresses, hereditary in two tests, reduced insignificantly after short-term annealing and reprogrammable, suggesting that the primary cause of bit upsets is charge loss of the floating gate in the memory cells. The memory cells with 25 nm feature size demonstrated a pronounced sensitivity to heavy ion irradiation, with a single ion strike on the sensitive volume capable of inducing a bit upset. Consequently, when the cumulative fluence remains significantly below the memory array’s density, the bit upset ratio exhibits a nearly linear correlation with the accumulation of heavy ion fluence. The study also identified that the severity of MCU events was proportional to the linear energy transfer (LET) of the incident ion, which led to a non-saturation effect in the SEU cross-section of NAND Flash memory, indicating that the Weibull fitting-based SEU cross-section evaluation method may not be appropriate for NAND Flash memory, or introduce significant errors. When programming the memory array to 55 h, the MCU topological patterns manifested as single vertical columns, double vertical columns, interval vertical columns, and so on, attributable to the interleaved bit line architecture of the memory array. Utilizing the ion track model, the effective radii of ion tracks for Ta, Ti, Al, and F were qualitatively estimated using experimental data from Ta. These estimated values align with the experimental observations of SEU cross-section and MCU statistics. It is postulated that in space applications, when the LET of the incident ion is sufficiently high or when adjacent bits within a byte are in a programming state, heavy ion incidence may induce multiple-bit upsets (MBU) within a single byte, posing additional challenges for error correction. The research further observed a decrease in the SEU cross-section with increasing fluence, particularly with Ti ions. This trend is attributed to the rapid decrease in the number of memory cells within the low voltage region of the programmed state threshold voltage distribution, which are centrally located on adjacent or nearby addresses, and the relatively unchanged growth rate of bit upsets in the remaining majority of memory cells. The relationship between SEU cross-section and heavy ion fluence suggests that irradiation at higher fluence may lead to an underestimation of the on-orbit bit upset rate for NAND Flash memory. Conversely, testing at lower fluence may yield a more conservative or accurate prediction of the on-orbit bit upset rate.