Abstract: Deep space exploration, nuclear industry and high energy physics raise higher requirements for the radiation hardness of integrated circuits. However, the existing radiation hardening technologies, such as radiation hardness by design based on bulk silicon technology or silicon-on insulator (SOI) process, are difficult to ensure that the electronics in spacecrafts and nuclear facilities function well in extreme space and nuclear radiation environments. In response to the lack of clear technical paths for the development of ultra-high radiation-hardened chip, a new type of highly radiation-hardened technique was introduced in this paper, named configurable SOI (CSOI). This technology innovatively employs twice bonding and cutting method to fabricate ultra-high radiation hardened 200 mm wafers with embedded configurable silicon layers. The 0-18 μm CSOI complementary metal oxide semiconductor (CMOS) process was successfully developed, which opens up a new route to achieve radiation hardness through in-situ radiation compensation. After the fabrication of CSOI devices, the configuration layer voltage can be tuned flexibly to compensate for the performance degradation due to total ionizing dose (TID) effect and simultaneously suppress the parasitic transistor effect triggered by single event effects (SEE). This helps to improve the radiation hardness of the CSOI transistors. Technology computer aided design (TCAD) simulations validate the tuning mechanism of configurable layer that a negative bias does good to the hardness of both TID and SEE in N-type MOSFET. Based on the CSOI process platform, a design methodology for integrated circuits was developed through assessing the impact of tuning granularity (down to transistor level) and range (from -20 V to 5 V) of configurable layer on the performance and radiation tolerance of static random-access memory (SRAM) cell. Then, the optimized tuning strategy of configurable layer was determined, and a CSOI 4kb SRAM was designed and fabricated with high radiation tolerance. The TID irradiation of the CSOI 4kb SRAM chip was performed at the ⁶⁰Co gamma irradiation source of Peking University and the SEE experiment was carried out at the Space Environment Simulation and Research Infrastructure (SESRI) in Harbin Institute of Technology. Radiation experiments confirm that the CSOI SRAM achieves up to a level of 6 Mrad(Si) for TID hardness and the threshold of single event upset is greater than 118 (MeV·cm²⁾/mg, which reaches world-class levels. It is expected to be applied in extreme fields such as deep space exploration and nuclear emergency.