Abstract: The demand for kilovolt-level radiation-hardened SiC devices in modern spacecraft is urgent. To provide a theoretical basis for the hardening design of SiC MOSFETs against single-event gate rupture (SEGR), a study on the single-event effects of 1 200 V asymmetric-trench SiC MOSFETs was conducted, analyzing the physical mechanisms of SEGR. The experimental samples were commercially available 1 200 V asymmetric-trench SiC MOSFETs. The heavy ion irradiation experiments were performed at Heavy Ion Research Facility in Lanzhou (HIRFL). The heavy ions used in the experiment were Ta ions, with a linear energy transfer (LET) value of 78.7 MeV/(mg/cm²) and a range of 80.5 μm in SiC material. During the experiment, two source measure units (SMUs) were employed to apply drain bias and gate bias, respectively, while monitoring and recording the drain leakage current (I_D) and gate leakage current (I_G). The gate bias was set to 0 V to maintain the device under test in the off-state, while the drain bias was set to a constant positive value to study the effects of drain bias on irradiation damage. In each irradiation process, the ion fluence rate was set to approximately 1×10⁴ cm⁻²·s⁻¹, with a total fluence of 1×10⁶ cm⁻². The experimental results show that both I_D and I_G exhibit degradation during irradiation at drain bias voltages of 200 V and 300 V. Additionally, I_D and I_G increase at the same rate as the heavy ion fluence increased. The post-irradiation measurements of the drain and gate characteristics are consistent with the trends observed during irradiation. TCAD simulations indicate that the transient electric field at the trench gate corner beneath the channel exceeds the critical breakdown field, and the damage to the gate oxide is identified as the primary cause of the leakage current degradation. However, at the trench gate corner surrounded by the P-well, the heavy doping of the P-type region facilitates the rapid extraction of holes, resulting in a weaker electric field concentration effect that does not reach the critical breakdown field. FIB-SEM results confirm that the oxide layer at the trench gate corner beneath the channel has been ruptured, causing direct contact between the gate polysilicon and the N⁻ drift region, forming a leakage current path from drain to gate. Therefore, the hardening design for trench-gate SiC MOSFETs against SEGR should focus on the trench gate corners and the trench bottom. Surrounding the trench gate corners with P-type regions can mitigate the electric field concentration effects caused by single-event effects. This study provides essential insights into the SEGR failure mechanisms in 1 200 V asymmetric-trench SiC MOSFETs, which are crucial for developing robust SiC devices for space applications.