Abstract: Temperature and supply voltage emerge as critical factors influencing single event upset (SEU) responses in nano-scale fully depleted silicon-on-insulator (FDSOI) technology. This paper conducted heavy ion radiation experiments on 22 nm FDSOI flip-flop circuit to obtain SEU cross section with temperature and supply voltage variations. Furthermore, TCAD simulations were also performed to study the single event effect (SEE) mechanisms of FDSOI device. To accurately capture the intrinsic SEU cross section data of FDSOI technology, commercial 22 nm FDSOI flip-flop was selected as the test sample. Based on HIRFL accelerator at the Institute of Modern Physics, Chinese Academy of Sciences, Ta ion (LET is 75.4 MeV·cm²/mg) was selected for the radiation experiments. Two temperature points (27 ℃ and 125 ℃) and two supply voltages (0.72 V and 0.88 V) were chosen to obtain the synergistic effect of temperature and supply voltage on SEU. Experimental results show that SEU cross section at high temperature increases by 40% compared to room temperature for 0.72 V supply voltage, while the value increases by 7% for the supply voltage of 0.88 V. The data demonstrates that the cross section increases with rising temperature at both low and high supply voltages. Moreover, the change in cross section at 0.72 V is 5.7 times higher than that at 0.88 V, which indicates that the temperature dependence of cross section is more pronounced at lower voltage. This difference can be fundamentally attributed to the combined effects of temperature and supply voltage on the charge collection (CC) mechanisms of the FDSOI device. To clarify the temperature and supply voltage dependence of cross section in flip-flop, 3D TCAD simulations were conducted, focusing on CC and saturation current (I_{_SAT}) under different temperature and supply voltage conditions. Initial TCAD models of NMOS and PMOS were established and the electrical characteristic curves exhibited close agreement with SPICE models. Simulation results show that CC is increased as temperature is raised from 27 ℃ to 125 ℃, confirming a positive correlation between CC and temperature. While the recovery capability is also improved at higher temperature, exerting opposing effects on SEE sensitivity compared with CC. Simulations reveal that the change in CC with temperature elevation, rather than I_{_SAT}, dominates the temperature and supply voltage dependence of SEU sensitivity. It is further demonstrated that for the same temperature range (27 ℃ to 125 ℃), reducing the supply voltage enhances the temperature-induced change in CC. The results address the synergistic effect of temperature and supply voltage on SEE susceptibility in nano-scale FDSOI circuits, it is also meaningful to SEE evaluation in dynamic supply voltage or temperature operating conditions and SEE hardened design requirements.